Objective To enhance the computational performance and energy efficiency ratio of object detection algorithms on edge hardware platforms under resource-constrained conditions this paper proposes and verifies an edge hardware platform based on field programmable gate array FPGA for accelerating the YOLOv4-tiny network. Methods High-level synthesis HLS was used to design and optimize the operators and modules of the algorithm in a highly parallel manner. To improve design throughput a double-buffering strategy was adopted to increase system resource utilization. Additionally techniques such as fusion of convolutional and batch normalization BN layers and model quantization were applied to reduce model parameters and enhance computational density. Results Experiments conducted on the PYNQZ2 platform demonstrate that the accelerator achieved a computational performance of 15. 33 GOPS with a total power consumption of 2. 65 W. Compared to existing FPGA platforms the proposed design improved computational performance by 2. 79 times while achieving a 29. 5-fold increase in energy efficiency ratio compared to CPU platforms. Conclusion The proposed method effectively enhances the acceleration of the YOLOv4-tiny network on edge FPGA platforms providing a valuable reference for the acceleration research of object detection algorithms on hardware platforms.