Objective Aiming at the issues of large hardware resource consumption and the relatively slow calculation speed of traditional bicubic interpolation scaling algorithms this study proposed a method to optimize hardware circuits using an improved bicubic interpolation algorithm based on common factor sharing. Methods This method involves constructing interpolation coefficient calculation formulas for bicubic interpolation. The common factor elimination method is employed to simplify the formulas aiming to extract common components and intermediate interpolation coefficients in the calculation of interpolation coefficients. Subsequently in the process of implementing hardware circuits these common components are merged for comprehensive calculation. Finally by representing the intermediate interpolation coefficients and integrating shared components an optimized bicubic interpolation circuit is constructed. Results Theoretical analysis shows that the number of multipliers is reduced from 36 to 20 thereby reducing hardware resource consumption. The constructed bicubic interpolation circuit is described using hardware description language and synthesized using AMD Xilinx?? s Vivado development tool. Experimental results demonstrate that the optimized bicubic interpolation circuit reduces 8% of the LUTs lookup tables 2% of the LUTRAMs and 14% of the DSP digital signal processor resources at the basic level. Conclusion The study proves that compared with existing optimization techniques the optimization method based on common factor sharing for bicubic interpolation algorithms can more effectively reduce hardware circuit resource consumption while maintaining image scaling quality.