A new parallel multiplier is designed by simple combinational logic circuits based on type I optimal normal basis and type Ⅱ optimal normal basis respectively.For the type I optimal normal basis，the parallel multiplier needs 3n4 XOR gates and n AND gates，for the type Ⅱ optimal normal basis，the parallel multiplier needs 2n2 XOR gates and n AND gates.Compared with the normal basis parallel multiplier based on type Ⅱ optimal normal basis proposed by Sunar and Koc in 2001，this multiplier greatly reduces required gates so as to effectively decrease the resources of consumption.