| 引用本文: | 完 海1 ,张肖强1 ,杨 帆1 ,郑辛星2.基于公共项共享的改进双三次插值算法电路研究(J/M/D/N,J:杂志，M：书，D：论文，N：报纸).期刊名称,2025，42（1）：112-122 |
| CHEN X. Adap tive slidingmode contr ol for discrete2ti me multi2inputmulti2 out put systems[ J ]. Aut omatica, 2006, 42(6): 4272-435 |
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| 摘要: |
| 目的 针对传统双三次插值缩放算法硬件资源消耗大、计算速度相对较慢的问题,提出一种利用公共项共享
的改进双三次插值算法硬件电路优化方法。 方法 该方法涉及构建双三次插值的插值系数计算公式,采用公因式消
除法简化公式,目的是提取插值系数计算中的公共成分和中间插值系数;随后,在硬件电路实施过程中,将这些公
共成分合并起来,进行综合计算;最终,通过对中间插值系数的表述和共享组件的整合,构建出一个优化的双三次
插值电路。 结果 理论分析表明:乘法器数量从 36 个减少到 20 个,从而降低了硬件资源消耗;所构建的双三次插值
电路使用硬件描述语言,并使用 AMD Xilinx 的 Vivado 开发工具进行综合。 实验结果表明:优化后的双三次插值电
路在基础层面上减少了 8%的 LUT( 查找表) 、2%的 LUTRAM 和 14%的 DSP( 数字信号处理器) 资源。 结论 事实证
明:与现有优化技术相比,基于公因子共享的双三次插值算法优化方法能更有效地减少硬件电路资源消耗,同时保
持图像缩放质量。 |
| 关键词: 双三次插值缩放算法 公共项共享 硬件电路优化 插值系数 |
| DOI： |
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| Research on Improved Bicubic Interpolation Algorithm Circuit Based on Common Factor Sharing |
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WAN Hai1 ZHANG Xiaoqiang1 YANG Fan1 ZHENG Xinxing2
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1. School of Electrical Engineering School of Integrated Circuits Anhui Polytechnic University Anhui Wuhu 241000
China
2. School of Information and Artificial Intelligence Wuhu Institute of Technology Anhui Wuhu 241000 China
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| Abstract: |
| Objective Aiming at the issues of large hardware resource consumption and the relatively slow calculation
speed of traditional bicubic interpolation scaling algorithms this study proposed a method to optimize hardware circuits
using an improved bicubic interpolation algorithm based on common factor sharing. Methods This method involves
constructing interpolation coefficient calculation formulas for bicubic interpolation. The common factor elimination method
is employed to simplify the formulas aiming to extract common components and intermediate interpolation coefficients in the calculation of interpolation coefficients. Subsequently in the process of implementing hardware circuits these
common components are merged for comprehensive calculation. Finally by representing the intermediate interpolation
coefficients and integrating shared components an optimized bicubic interpolation circuit is constructed. Results
Theoretical analysis shows that the number of multipliers is reduced from 36 to 20 thereby reducing hardware resource
consumption. The constructed bicubic interpolation circuit is described using hardware description language and
synthesized using AMD Xilinx?? s Vivado development tool. Experimental results demonstrate that the optimized bicubic
interpolation circuit reduces 8% of the LUTs lookup tables 2% of the LUTRAMs and 14% of the DSP digital signal
processor resources at the basic level. Conclusion The study proves that compared with existing optimization techniques
the optimization method based on common factor sharing for bicubic interpolation algorithms can more effectively reduce
hardware circuit resource consumption while maintaining image scaling quality. |
| Key words: bicubic interpolation scaling algorithm common factor sharing hardware circuit optimization interpolation
coefficient |
