| 摘要: |
| 利用简单的组合逻辑电路分别在Ⅰ型和Ⅱ型最优正规基上设计出了新的并行乘法器，其中Ⅰ型最优正规基并行乘法器所需异或门数为3n-4，与门数为n，Ⅱ型最优正规基并行乘法器所需异或门数为2n-2，与门数为n；与Sunar和Koc于2001年在Ⅱ型最优正规基上提出的并行正规基乘法器对照，此乘法器大大减少了所需要的门数，从而有效地降低了硬件消耗的资源. |
| 关键词: 有限域 最优正规基 乘法器 门数 |
| DOI： |
| 分类号: |
| 基金项目: |
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| Parallel Multiplier Design based on optimal Normal Basis |
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SU Dan dan1，FU Ping2
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| Abstract: |
| A new parallel multiplier is designed by simple combinational logic circuits based on type I optimal normal basis and type Ⅱ optimal normal basis respectively.For the type I optimal normal basis，the parallel multiplier needs 3n 4 XOR gates and n AND gates，for the type Ⅱ optimal normal basis，the parallel multiplier needs 2n 2 XOR gates and n AND gates.Compared with the normal basis parallel multiplier based on type Ⅱ optimal normal basis proposed by Sunar and Koc in 2001，this multiplier greatly reduces required gates so as to effectively decrease the resources of consumption. |
| Key words: finite fields optimal normal basis multipliers gates |
