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| 摘要: |
| 介绍了高速PCB设计中的信号完整性概念以及影响信号完整性的因素和不完整性形成原因；从传输线理论的层面上重点分析了高速电路设计中反射和串扰的形成机制并提出了解决办法；基于IBIS模型实现了对ARM9SC2410×01芯片的时钟输出引脚的仿真，给出了IBIS模型仿真步骤。 |
| 关键词: 信号完整性 反射 串扰 IBIS仿真 |
| DOI： |
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| The High-Speed PCB Based Signal Intergrity Analysis |
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LIU Jian-ping
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| Abstract: |
| The concept of signal integrity and causes of signal integrity issue in the high-speed PCB design are introduced.Based on transmission line theory,the formation mechanism of the reflection and crosstalk in the high-speed design is intensively analyzed and solutions are proposed.Based on IBIS model,a simulation of the ARM9S2C2410XO1 chip's clock signal output pin is realized and the IBIS model simulation steps are provided. |
| Key words: sigal integrity reflection crosstalk IBIS simulation |
